UPSC 2026 Maths Optional Paper 2 Q5c — Step-by-Step Solution
10 marks · Section B
Question
Consider the logic circuit : inputs , , feed three AND gates whose outputs feed a single OR gate producing . The first AND gate receives , and directly; the second receives , (via an inverter on the line) and ; the third receives (via an inverter on the line) and .
(i) Express as a Boolean expression.
(ii) Write 8-bit special sequences for , and .
(iii) Find the truth table of using 8-bit special sequences.
(In the printed paper this is the only figure: a gate diagram. The wiring above is the transcription of that diagram — three AND gates feeding one OR gate, with AND-3 taking exactly two inputs, and .)
The circuit as printed in the paper (UPSC CSM 2026 Paper II, Q5(c)). The prose above is the accessible-text transcription of this diagram; the two must agree exactly — in particular AND-3 has two inputs, not three.
Technique
Read the sum-of-products straight off the circuit — one product term per AND gate, OR-ed together — then simplify before tabulating: the first two terms differ only in and , so the complementation law collapses them at once. For part (iii) the “special sequences” technique replaces row-by-row evaluation with eight parallel evaluations done as bitwise operations on 8-bit words; the whole truth table then falls out as a single output word, and the answer must show the bitwise columns, because that is the technique being examined.
Solution
Step 0 — Read the circuit.
| gate | inputs | output |
|---|---|---|
| AND-1 | ||
| AND-2 | ||
| AND-3 | (two inputs only) | |
| OR | the three AND outputs |
(i) The Boolean expression.
An AND gate outputs the product of its inputs and an OR gate the sum of its inputs, so
Simplify. The first two terms share the factor :
using the complement law and the identity . Hence
This is minimal. The minterms of are (established in (iii) below); on a three-variable K-map the prime implicants are (cells ), (cells ) and (cells ). Cell is covered only by and cell only by , so both are essential, and together they already cover all four cells. Therefore is the unique minimal sum of products, and the consensus term is redundant:
(Redundant logically, but the term one would add back to make the hardware free of a static-1 hazard when switches with — one line, and it shows the circuit is understood, not just the algebra.)
Interpretation. is precisely a 2-to-1 multiplexer with as the select line: when and when . Gate count drops from AND OR NOT (with a 3-input OR-free 3-input AND) to AND OR NOT.
(ii) The 8-bit special sequences.
Convention (must be stated, since the sequences depend on it). For variables there are input combinations. List them as the rows of the truth table in ascending binary order with as the most significant bit:
Reading each variable down its column gives its 8-bit special (standard/distinctive) sequence. For the -th of variables the sequence is alternating blocks of zeros and ones; with :
Bit position (, read left to right) of every sequence refers to the same input combination, namely the binary representation of — that is the whole point of the device.
(iii) The truth table by bitwise operations on the sequences.
Complements are bitwise NOT:
Now form the three AND-gate outputs by bitwise AND and the OR-gate output by bitwise OR. Working the unsimplified expression (1) — which is what the circuit actually builds — and, in parallel, the simplified expression (2), as a self-check:
| word | bit 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 |
In compact sequence form:
and by the simplified route
The two routes give the identical word, which confirms the simplification (2) — a free check the technique hands you.
Reading the truth table off the output sequence. Bit of is the output for the row whose is the binary form of :
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 0 |
| 5 | 1 | 0 | 1 | 1 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 1 |
So , as used in the K-map argument of part (i). Sanity spot-checks against : row gives ✓; row gives ✓; row gives ✓. And the multiplexer reading is visible in the table: for (rows –) copies ; for (rows –) copies .
Answer
with truth table for respectively.